The inventive concept relates to a system for verifying a system on a chip (SoC) including one or more IPs, and more particularly, to an SoC device verification system for connecting an internal IP verification model of an SoC device and an external IP verification model by using a memory controller included by an SoC. IPs are circuit design modules or design objects that are commonly employed in SoC design. A collection of IPs, each of a known function, and each being modeled and pre-tested for performance and functionality, can be joined in an SoC design to create a device of greater functionality.
A system on a chip (SoC) is a device whereby all components of an electronic system are integrated onto a single integrated chip. It is common for SoC devices to initially include an integrated processor and a few IPs during an initial stage of development. However, during later stages of development, it is common for most SoC devices to include several tens of IPs as a part of the design process using various computer aided engineering (CAE) tools. As SoC integration continues to improve, the SoC devices increase in size and functionality, and therefore, include an ever-increasing number of IPs. Therefore, it continues to become more important to reduce SoC device development time.